1. Field of the Invention
The present invention relates to a novel digital time error generator of the type employed to produce an error signal indicative of the difference between sampling time and the data transition time. More particularly, the present invention relates to a time error generator for producing a digital sample rate frequency command employed by a clock synthesizer and the timing and control circuits, which are synchronized with the data signal transitions received by a communication receiver.
2. Description of the Prior Art
Heretofore, digital time error signal generators have been proposed for use in communication receivers, such proposed systems have employed separate off the shelf timing and control modules which are not programmable by frequency commands, accordingly, there is no known prior art digital error signal generator circuitry known to have been integrated into a very large scale integrated circuit communications receiver.
There is an unmet need for a complete on chip digital time error signal generator capable of being programmed for generating digital commands which may be applied to conventional off chip digital clock synthesizers of the type employed with on chip timing and control circuits of digital communication receivers.